A synchronous first-in first-out (FIFO) buffer can include logic indicating when the FIFO is half-full. In a typical synchronous FIFO, the half-full status flag is updated by a single clock, typically a write clock. The logic to generate the half-full flags typically consists of counters, adders, combinatorial logic to generate a so called internal half-full flag and a final output register. An alternate way to generate the internal half-full flag is by directly decoding the counter outputs using combinatorial logic. A register is implemented which is typically a master-slave register. Typically the half-full flag is updated by the write clock.
The minimum delay between the clocks is defined as a tSKEW delay. An updating clock, either the write or read clock, is guaranteed to recognize the second clock, either the read or write clock, if it occurs at least tSKEW delay ahead of the updating clock. If the second (read) clock occurs within tSKEW time from the updating clock (write), the updating clock may or may not recognize the second clock.
Previous approach architectures suffer from very high tSKEW delays (.about.8-10 Gate Delays). Additionally these architectures also suffer from metastabilty problems introduced by the register trying to sample the asynchronous internal flag which is updated by both the asynchronous read and write clocks. The present invention solves both of these issues by providing very high MTBF and very short, even Ons tSKEW. Additionally the present invention gives designers the flexibility to program the tSKEW to any desired value, including a Ons tSKEW.